1. Field of the Invention
The invention relates to a method for the production of a semiconductor component, particularly a pHEMT field effect transistor, having a metallic gate electrode disposed in a double-recess structure.
2. The Prior Art
Semiconductor elements having a gate electrode disposed in a double-recess structure, are known in various embodiments.
In U.S. Pat. No. 5,796,132, the two recesses are assigned to one another by adjustment, and masked by a resist mask or SiN hard mask during etching. Furthermore, isolation is possible, in the case of a pHEMT (Pseudomorphic High Electron Mobility Transistor), only by over-etching on a stop layer. This results in cavities that later can no longer be passivated. The T-shaped gate head is formed, in the method shown, by the etching of a metallization deposited on the entire area. In U.S. Pat. No. 5,556,797, the two recesses are formed self-adjusted relative to one another, but it is not possible to form a low-ohm T-shaped gate head, which is, however, required for high-frequency applications. The same also holds true for U.S. Pat. No. 5,641,977.
U.S. Patent Application Publication No. 2004/0082158 A1 describes a method in which several photo-resist layers are deposited onto the semiconductor layer sequence, in which layers structures for the gate head are prepared, using the lift-off method, for the subsequent production of a T-shaped gate electrode. In the lowermost resist layer, deposited onto the highly doped contact layer of the semiconductor layer sequence, an opening that determines the structure of the gate foot is produced. The resist layers are maintained during the subsequent method steps, up to vapor deposition of the gate metal. Under the lowermost resist layer, a recess structure is produced in the contact layer, by under-etching, up to a barrier layer, and gate metal is deposited through the opening of the lowermost resist layer, to form the gate foot on the barrier layer, and, at the same time, deposited in the structures of the upper resist layers, to form the gate head. The gate electrode is exposed by dissolving the resist layers. Afterwards, ohmic contacts are still produced on the highly doped contact layer.